189 radhard msi logic UT54ACS273/ut54acts273 radiation-hardened octal d-flip-flops with clear features contains eight flip-flops with single-rail outputs buffered clock and direct clear inputs individual data input to each flip-flop applications include: - buffer/storage registers, shift registers, and pattern generators radiation-hardened cmos - latchup immune high speed low power consumption single 5 volt supply available qml q or v processes flexible package - 20-pin dip - 20-lead flatpack description the UT54ACS273 and the ut54acts273 are positive-edge- triggered d-type flip-flops with a direct clear input. information at the d inputs meeting the setup time requirements is transferred to the q outputs on the positive-going edge of the clock pulse. when the clock input is at either the high or low level, the d input signal has no effect at the output. the devices are characterized over full military temperature range of -55 c to +125 c. function table pinouts 20-pin dip top view 20-lead flatpack top view logic symbol inputs outputs clr clk d x q x l x x l h h h l h l x h l no change 1 2 3 4 5 7 6 20 19 18 17 16 14 15 clr 1q 1d 2d 2q 3q 3d v dd 8q 8d 7d 7q 6d 8 13 4d 5d 6q 9 12 4q 5q 10 11 v ss clk 1 2 3 4 5 7 6 20 19 18 17 16 14 15 clr 1q 1d 2d 2q 3q 3d v dd 8q 8d 7d 7q 6d 8 13 4d 5d 6q 9 12 4q 5q 10 11 v ss clk (1) clr (11) clk c1 r (3) 1d (4) 2d (2) 1q (6) 3q (9) 4q (12) 5q (15) 6q (16) 7q (19) 8q 1d (7) 3d (8) 4d (13) 5d (14) 6d (17) 7d (18) 8d (5) 2q note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12.
radhard msi logic 190 UT54ACS273/ut54acts273 logic diagram radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, fun ctional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 1d (3) 1q (2) 2d (4) 2q (5) 3d (7) 3q (6) 4d (8) 4q (9) 5d (13) 5q (12) 6d (14) 6q (15) 7d (17) 7q (16) 8d (18) 8q (19) c (11) (1) clr clk d r c d r c d r c d r c d r c d r c d r c d r symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w
191 radhard msi logic UT54ACS273/ut54acts273 recommended operating conditions symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
radhard msi logic 192 UT54ACS273/ut54acts273 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 = 1mhz @ 0v 15 pf c out output capacitance 5 = 1mhz @ 0v 15 pf
193 radhard msi logic UT54ACS273/ut54acts273 notes: 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
radhard msi logic 194 UT54ACS273/ut54acts273 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1 , -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh clk to q 4 17 ns t phl clk to q 4 19 ns t phl clr to q 5 19 ns f max maximum clock frequency 63 mhz t su1 clr inactive setup time before clk 5 ns t su2 data setup time before clk 5 ns t h data hold time after clk 3 ns t w minimum pulse width clr low clk high clk low 8 ns
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